Implement Mstatus.bits()

riscv/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add `Mcause::from(usize)` for use in unit tests
+- Add `Mstatus.bits()`
 
 ### Fixed
 

riscv/src/register/mstatus.rs

@@ -65,6 +65,12 @@ impl From<bool> for Endianness {
 }
 
 impl Mstatus {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(&self) -> usize {
+        self.bits
+    }
+
     /// Supervisor Interrupt Enable
     #[inline]
     pub fn sie(&self) -> bool {